Testing within the integrated circuit (IC) industry is a process of verification that the device manufactured is functionally acceptable to customer. The integrated circuit (IC) industry tests every IC devices before shipping to customers. In a test process, there are many test methods available to catch various defects introduced from the process and design. There was a point in time when the IC industry did not perform full coverage testing and performed sampling of IC devices in testing prior to shipping to customers to minimize the cost. However, as the technology node shrinks and process marginalities become smaller, practices such as sampling has been phased out and testing every one of the manufactured ICs has become the norm. Furthermore, the IC industry practices widest coverage testing to provide best quality manufactured ICs. With the progression of such changes, the cost associated with testing has become a significant factor in manufacturing an IC.
The IC industry typically uses a parallel delivery method to deliver scan test data into the ICs. The parallel delivery method provides scan test data directly to each of the inputs and outputs (IOs) of the device under test (DUT). So far, the parallel delivery method has provided an efficient manner to check each input and output (IO) of the DUT and provides feedback on the corresponding functionality. The parallel delivery method drives a signal from each tester 10 or driver to the designated 10 on the IC and then reads back the response from the IC.
There are drawbacks associated with parallel delivery method. For example, each 10 on the DUT requires an independent 10 or driver resource from the tester. Such a requirement poses problems when it comes to larger devices with multiple IOs. Furthermore, test interface from the tester resource to the DUT requires advanced technologies when testing a large device with multiple IOs. A common problem observed during the design of the test interface at the tester for the large devices using parallel data delivery is tight pitch trace requirements while maintaining adequate interconnection speed requirements. Balancing between these requirements incurs significantly higher testing cost due to their inverse relationship.
It is within this context that the embodiments described herein arise.